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| TM HIP6021A Data Sheet December 2001 FN4793.1 Advanced PWM and Triple Linear Power Controller The HIP6021A provides the power control and protection for four output voltages in high-performance, graphics intensive microprocessor and computer applications. The IC integrates a voltage-mode PWM controller and three linear controllers, as well as the monitoring and protection functions into a 28 lead SOIC package. The synchronous-rectified buck converter includes an Intelcompatible, TTL 5-input digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 1.3VDC to 2.05VDC in 0.05V steps and from 2.1VDC to 3.5VDC in 0.1V increments. The precision reference and voltage-mode control provide 1% static regulation. A TTL-compatible signal applied to the SELECT pin dictates which method of control is used for the AGP bus power: a low state results in linear control of the AGP bus to 1.5V, while a high state transitions the output through a linearly controlled softstart to 3.3V, followed by full enhancement of the external MOSFET to pass the input voltage. The other two linear regulators provide fixed output voltages of 1.5V GTL bus power and 1.8V power for the North/South Bridge core and/or cache memory. These levels are user-adjustable by means of an external resistor divider and pulling the FIX pin low. All linear controllers can employ either N-Channel MOSFETs or bipolar NPNs for the pass transistor. The HIP6021A monitors all the output voltages. A single Power Good signal is issued when the core is within 10% of the DAC setting and all other outputs are above their undervoltage levels. Additional built-in over-voltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM controller's over-current function monitors the output current by using the voltage drop across the upper MOSFET's rDS(ON). Features * Provides 4 Regulated Voltages - Microprocessor Core, AGP Bus, Memory, and GTL Bus Power * Drives N-Channel MOSFETs * Linear Regulator Drives Compatible with both MOSFET and Bipolar Series Pass Transistors * Fixed or Externally Resistor-Adjustable Linear Outputs * Simple Single-Loop Control Design - Voltage-Mode PWM Control * Fast PWM Converter Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio * Excellent Output Voltage Regulation - Core PWM Output: 1% Over Temperature - Other Outputs: 3% Over Temperature * TTL-Compatible 5-Bit DAC Core Output Voltage Selection - Shutdown Feature Removed When All Inputs High - Wide Range 1.3VDC to 3.5VDC * Power-Good Output Voltage Monitor * Over-Voltage and Over-Current Fault Monitors - Switching Regulator Does Not Require Extra Current Sensing Element, Uses Upper MOSFET's rDS(ON) * Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator; Programmable From 50kHz to Over 1MHz - Small External Component Count Applications * Motherboard Power Regulation for Computers Pinout HIP6021A (SOIC) TOP VIEW DRIVE2 1 FIX 2 VID4 3 VID3 4 VID2 5 VID1 6 VID0 7 PGOOD 8 SD 9 VSEN2 10 SELECT 11 SS 12 FAULT/RT 13 VSEN4 14 28 VCC 27 UGATE 26 PHASE 25 LGATE 24 PGND 23 OCSET 22 VSEN1 21 FB 20 COMP 19 VSEN3 18 DRIVE3 17 GND 16 VAUX 15 DRIVE4 Ordering Information PART NUMBER HIP6021ACB HIP6021EVAL1 TEMP. RANGE (oC) 0 to 70 PACKAGE 28 Ld SOIC PKG. NO. M28.3 Evaluation Board 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001. All Rights Reserved Block Diagram VSEN3 FIX SD VSEN1 OCSET VCC VAUX POWER-ON x 1.10 RESET (POR) + x 0.90 + + 1.26V LINEAR UNDERVOLTAGE + x 1.15 LUV + PGOOD 200A + x 0.75 OV SOFTINHIBIT START AND FAULT FAULT LOGIC OC1 + ERROR AMP1 + + GATE CONTROL PWM COMP1 PWM1 VCC LGATE SYNCH DRIVE DACOUT PGND GND + VCC 28A OSCILLATOR 4.5V TTL D/A CONVERTER (DAC) FAULT / RT SS FB COMP VID0 VID1 VID2 VID4 VID3 VAUX HIP6021A VSEN2 + SELECT - 1.5V OR 3.3VIN + 2 DRIVE3 + DRIVE4 + - VSEN4 DRIVE1 VCC UGATE PHASE DRIVE2 x 0.75 HIP6021A Simplified Power System Diagram +5VIN +3.3VIN LINEAR CONTROLLER PWM CONTROLLER Q2 Q1 Q3 VOUT2 VOUT1 HIP6021A VOUT3 Q4 LINEAR CONTROLLER LINEAR CONTROLLER Q5 VOUT4 Typical Application +12VIN +5VIN LIN CIN VCC OCSET +3.3VIN PGOOD VOUT2 1.5V OR 3.3VIN Q3 DRIVE2 VSEN2 POWERGOOD UGATE PHASE Q1 LOUT1 VOUT1 1.3V TO 3.5V COUT2 LGATE SELECT VAUX PGND VSEN1 Q2 COUT1 TYPEDET HIP6021A VOUT3 1.5V Q4 DRIVE3 VSEN3 FB COMP COUT3 FIX FAULT / RT VID0 Q5 VOUT4 1.8V DRIVE4 VSEN4 SS CSS GND VID1 VID2 VID3 COUT4 VID4 3 HIP6021A Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V PGOOD, RT/FAULT, DRIVE, PHASE, and GATE Voltage . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . 0oC to 125oC SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER VCC SUPPLY CURRENT Nominal Supply Current POWER-ON RESET Rising VCC Threshold Falling VCC Threshold Rising VAUX Threshold VAUX Threshold Hysteresis Rising VOCSET Threshold OSCILLATOR Free Running Frequency Total Variation Ramp Amplitude Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ICC UGATE, LGATE, DRIVE2, DRIVE3, and DRIVE4 Open - 9 - mA VOCSET = 4.5V VOCSET = 4.5V VOCSET = 4.5V VOCSET = 4.5V 8.2 - 2.5 0.5 1.26 10.4 - V V V V V FOSC RT = OPEN 6k < RT to GND < 200k 185 -15 - 200 1.9 215 +15 - kHz % VP-P VOSC RT = Open DAC AND BANDGAP REFERENCE DAC(VID0-VID4) Input Low Voltage DAC(VID0-VID4) Input High Voltage DACOUT Voltage Accuracy Bandgap Reference Voltage Bandgap Reference Tolerance LINEAR REGULATORS (OUT2, OUT3, AND OUT4) Regulation (All Linears) VSEN2 Regulation Voltage VSEN3 Regulation Voltage VSEN4 Regulation Voltage Under-Voltage Level (VSEN/VREG) Under-Voltage Hysteresis (VSEN/VREG) Output Drive Current (All Linears) VREG2 VREG3 VREG4 VSENUV VSEN Rising VSEN Falling VAUX-VDRIVE > 0.6V Except OUT2 when SELECT > 2.0V SELECT < 0.8V 20 3 1.5 1.5 1.8 75 7 40 % V V V % % mA VBG 2.0 -1.0 -2.5 1.265 0.8 +1.0 +2.5 V V % V % 4 HIP6021A Electrical Specifications PARAMETER Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate PWM CONTROLLER GATE DRIVER UGATE Source UGATE Sink LGATE Source LGATE Sink PROTECTION VSEN1 Over-Voltage (VSEN1/DACOUT) FAULT Sourcing Current OCSET1 Current Source Soft-Start Current POWER GOOD VSEN1 Upper Threshold (VSEN1/DACOUT) VSEN1 Under-Voltage (VSEN1/DACOUT) VSEN1 Hysteresis (VSEN1/DACOUT) PGOOD Voltage Low VPGOOD VSEN1 Rising VSEN1 Rising Upper/Lower Threshold IPGOOD = -4mA 108 92 2 110 94 0.8 % % % V IOVP IOCSET ISS VSEN1 Rising VFAULT/RT = 2.0V VOCSET = 4.5VDC 170 115 8.5 200 28 120 230 % mA A A IUGATE RUGATE ILGATE RLGATE VCC = 12V, VUGATE = 6V VGATE-PHASE = 1V VCC = 12V, VLGATE = 1V VLGATE = 1V 1 1.7 1 1.4 3.5 3.0 A A GBWP SR COMP = 10pF 88 15 6 dB MHz V/s Typical Performance Curve 1000 RESISTANCE (k) RT PULLUP TO +12V 100 10 RT PULLDOWN TO VSS 10 100 SWITCHING FREQUENCY (kHz) 1000 FIGURE 1. RT RESISTANCE vs FREQUENCY 5 HIP6021A Functional Pin Descriptions VCC (Pin 28) Provide a 12V bias supply for the IC to this pin. This pin also provides the gate bias charge for all the MOSFETs controlled by the IC. The voltage at this pin is monitored for Power-On Reset (POR) purposes. the soft-start capacitor, disabling all the outputs. Dedicated internal circuitry insures the core output voltage does not go negative during this process. When re-enabled, the IC undergoes a new soft-start cycle. Left open, this pin is pulled low by an internal pull-down resistor, enabling operation. FIX (Pin 2) Grounding this pin bypasses the internal resistor dividers that set the output voltage of the 1.5V and 1.8V linear regulators. This way, the output voltage of the two regulators can be adjusted from 1.26V up to the input voltage (+3.3V or +5V) by way of an external resistor divider connected at the corresponding VSEN pin. The new output voltage set by the external resistor divider can be determined using the following formula: R OUT V OUT = 1.265V x 1 + ---------------- R GND GND (Pin 17) Signal ground for the IC. All voltage levels are measured with respect to this pin. PGND (Pin 24) This is the power ground connection. Tie the synchronous PWM converter's lower MOSFET source to this pin. VAUX (Pin 16) This pin provides boost current for the linear regulators' output drives in the event bipolar NPN transistors (instead of N-Channel MOSFETs) are employed as pass elements. The voltage at this pin is monitored for power-on reset (POR) purposes. SS (Pin 12) Connect a capacitor from this pin to ground. This capacitor, along with an internal 28A current source, sets the softstart interval of the converter. where ROUT is the resistor connected from VSEN to the output of the regulator, and RGND is the resistor connected from VSEN to ground. Left open, the FIX pin is pulled high, enabling fixed output voltage operation. VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3) VID0-4 are the TTL-compatible input pins to the 5-bit DAC. The logic states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the microprocessor core converter output voltage, as well as the corresponding PGOOD and OVP thresholds. FAULT / RT (Pin 13) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: 5 x 10 Fs 200kHz + -------------------R T ( k ) 6 OCSET (Pin 23) Connect a resistor from this pin to the drain of the respective upper MOSFET. This resistor, an internal 200A current source, and the upper MOSFET's on-resistance set the converter over-current trip point. An over-current trip cycles the soft-start function. The voltage at this pin is monitored for power-on reset (POR) purposes and pulling this pin low with an open drain device will shutdown the IC. (RT to GND) Conversely, connecting a resistor from this pin to VCC reduces the switching frequency according to the following equation: 4 x 10 Fs 200kHz - -------------------R T ( k ) 7 (RT to 12V) PHASE (Pin 26) Connect the PHASE pin to the PWM converter's upper MOSFET source. This pin represents the gate drive return current path and is used to monitor the voltage drop across the upper MOSFET for over-current protection. Nominally, the voltage at this pin is 1.26V. In the event of an over-voltage or over-current condition, this pin is internally pulled to VCC. PGOOD (Pin 8) PGOOD is an open collector output used to indicate the status of the output voltages. This pin is pulled low when the synchronous regulator output is not within 10% of the DACOUT reference voltage or when any of the other outputs are below their under-voltage thresholds. The PGOOD output is open for `11111' VID code. UGATE (Pin 27) Connect UGATE pin to the PWM converter's upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. LGATE (Pin 25) Connect LGATE to the PWM converter's lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. SD (Pin 9) This pin shuts down all the outputs. A TTL-compatible, logic level high signal applied at this pin immediately discharges 6 HIP6021A COMP and FB (Pin 20 and 21) COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter. The microprocessor core voltage (VOUT1) is controlled in a synchronous-rectified buck converter configuration. The PWM controller regulates the microprocessor core voltage to a level programmed by the 5-bit digital-to-analog converter (DAC). The AGP bus voltage (VOUT2) is set using the SELECT pin to either a 1.5V linear regulated output or to the 3.3VIN through a pass device. Selection of either output voltage is set depending on the logic level of the SELECT pin. The two remaining linear controllers supply the 1.5V GTL bus power (VOUT3) and the 1.8V memory power (VOUT4). These output voltages are user adjustable. All linear controllers are designed to employ an external pass transistor. VSEN1 (Pin 22) This pin is connected to the PWM converter's output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over-voltage protection. DRIVE2 (Pin 1) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the AGP regulator's pass transistor. VSEN2 (Pin 10) Connect this pin to the output of the AGP linear regulator. The voltage at this pin is regulated to the level predetermined by the logic-level status of the SELECT pin. This pin is also monitored for under-voltage events. Initialization The HIP6021A automatically initializes upon receipt of input power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage (+12VIN) at the VCC pin, the 5V input voltage (+5VIN) on the OCSET pin, and the 3.3V input voltage (+3.3VIN) at the VAUX pin. The normal level on OCSET is equal to +5VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft-start operation after all supply voltages exceed their POR thresholds. SELECT (Pin 11) This pin determines the output voltage of the AGP bus linear regulator. A low TTL input sets the output voltage to 1.5V and the linear controller regulates this voltage to within 3%. A TTL high input turns Q3 on continuously, providing a DC current path from the input (+3.3VIN) to the output (VOUT2) of the AGP controller. Soft-Start The POR function initiates the soft-start sequence. Initially, the voltage on the SS pin rapidly increases to approximately 1V (this minimizes the softstart interval). Then an internal 28A current source charges an external capacitor (CSS) on the SS pin to 4.5V. The PWM error amplifier reference input (+ terminal) and output (COMP pin) are clamped to a level proportional to the SS pin voltage. As the SS pin voltage slews from 1V to 4V, the output clamp allows generation of PHASE pulses of increasing width that charge the output capacitor(s). After the output voltage increases to approximately 70% of the set value, the reference input clamp slows the output voltage rate-of-rise and provides a smooth transition to the final set voltage. Additionally, all linear regulators' reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a rapid and controlled output voltage rise. Figure 2 shows the soft-start sequence for the typical application. At T0 the SS voltage rapidly increases to approximately 1V. At T1, the SS pin and error amplifier output voltage reach the valley of the oscillator's triangle wave. The oscillator's triangular waveform is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse width on the PHASE pin increases. The interval of increasing pulse width continues until each output reaches sufficient voltage to transfer control to the input reference clamp. If we consider the 2.5V core output (VOUT1) in Figure 2, this time occurs at DRIVE3 (Pin 18) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.5V regulator's pass transistor. VSEN3 (Pin 19) Connect this pin to the output of the 1.5V linear regulator. This pin is monitored for under-voltage events. DRIVE4 (Pin 15) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.8V regulator's pass transistor. VSEN4 (Pin 14) Connect this pin to the output of the linear 1.8V regulator. This pin is monitored for under voltage events. Description Operation The HIP6021A monitors and precisely controls 4 output voltage levels (Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic). It is designed for microprocessor computer applications with 3.3V, 5V, and 12V bias input from an ATX power supply. 7 HIP6021A T2. During the interval between T2 and T3, the error amplifier reference ramps to the final value and the converter regulates the output a voltage proportional to the SS pin voltage. At T3 the input clamp voltage exceeds the reference voltage and the output voltage is in regulation. linear output (VSEN2, VSEN3, or VSEN4) is ignored until after the soft-start interval (T4 in Figure 2). This allows VOUT2 , VOUT3 , and VOUT4 to increase without fault at startup. Cycling the bias input voltage (+12VIN on the VCC pin off then on) resets the counter and the fault latch. LUV PGOOD 0V OC1 SOFT-START (1V/DIV) 0.15V + OVERCURRENT LATCH SQ R INHIBIT - COUNTER R UP POR FAULT LATCH SQ R VCC 0V VOUT2 (= 3.3VIN) SS 4V OV + - FAULT VOUT1 (DAC = 2.5V) VOUT4 (= 1.8V) OUTPUT VOLTAGES (0.5V/DIV) FIGURE 3. FAULT LOGIC - SIMPLIFIED SCHEMATIC VOUT3 (= 1.5V) Over-Voltage Protection During operation, a short on the upper MOSFET of the PWM regulator (Q1) causes VOUT1 to increase. When the output exceeds the over-voltage threshold of 115% of DACOUT, the over-voltage comparator trips to set the fault latch and turns Q2 on. This blows the input fuse and reduces VOUT1. The fault latch raises the FAULT/RT pin to VCC. A separate over-voltage circuit provides protection during the initial application of power. For voltages on the VCC pin below the power-on reset (and above ~4V), the output level is monitored for voltages above 1.3V. Should VSEN1 exceed this level, the lower MOSFET, Q2 is driven on. 0V T0 T1 T2 T3 T4 TIME FIGURE 2. SOFT-START INTERVAL The remaining outputs are also programmed to follow the SS pin voltage. The PGOOD signal toggles `high' when all output voltage levels have exceeded their under-voltage levels. The waveform for VOUT2 represents the case where SELECT is held `high'. The AGP bus voltage is controlled in the same manner as the other linear regulators during the softstart sequence. Once the softstart sequence is complete (T4), the gate of the external pass device is fully enhanced and VOUT2 tracks the 3.3VIN voltage. See the Soft-Start Interval section under Applications Guidelines for a procedure to determine the soft-start interval. Over-Current Protection All outputs are protected against excessive over-currents. The PWM controller uses the upper MOSFET's on-resistance, rDS(ON) to monitor the current for protection against shorted output. All linear controllers monitor their respective VSEN pins for under-voltage events to protect against excessive currents. Figure 4 illustrates the over-current protection with an overload on OUT1. The overload is applied at T0 and the current increases through the inductor (LOUT1). At time T1, the OVER-CURRENT comparator trips when the voltage across Q1 (iD * rDS(ON)) exceeds the level programmed by ROCSET. This inhibits all outputs, discharges the soft-start capacitor (CSS) with a 10mA current sink, and increments the counter. CSS recharges at T2 and initiates a soft-start cycle with the error amplifiers clamped by soft-start. With OUT1 still overloaded, the inductor current increases to trip the over-current comparator. Again, this inhibits all outputs, but the soft-start voltage continues increasing to 4V before discharging. The counter increments to 2. The soft-start cycle repeats at T3 and trips the over-current comparator. Fault Protection All four outputs are monitored and protected against extreme overload. A sustained overload on any output or an overvoltage on VOUT1 output (VSEN1) disables all outputs and drives the FAULT/RT pin to VCC. Figure 3 shows a simplified schematic of the fault logic. An over-voltage detected on VSEN1 immediately sets the fault latch. A sequence of three over-current fault signals also sets the fault latch. The over-current latch is set dependent upon the states of the over-current (OC), linear undervoltage (LUV) and the soft-start signals. A window comparator monitors the SS pin and indicates when CSS is fully charged to 4V (UP signal). An under-voltage on either 8 HIP6021A The SS pin voltage increases to 4V at T4 and the counter increments to 3. This sets the fault latch to disable the converter. The fault is reported on the FAULT/RT pin. The linear controllers operate in the same way as the PWM in response to over-current faults. The differentiating factor for the linear controllers is that they monitor the VSEN pins for under-voltage events. Should excessive currents cause the voltage at the VSEN pins to fall below the linear undervoltage threshold, the LUV signal sets the over-current latch if CSS is fully charged. Blanking the LUV signal during the CSS charge interval allows the linear outputs to build above the under-voltage threshold during normal operation. Cycling the bias input power off then on resets the counter and the fault latch. OVER-CURRENT TRIP: V >V DS SET i xr D DS ( ON ) > I OCSET x R OCSET OCSET IOCSET 200A OVERCURRENT OC + VCC DRIVE UGATE PHASE V PWM GATE CONTROL = V -V PHASE IN DS V = V -V OCSET IN SET + VDS ROCSET VSET + iD VIN = +5V - FIGURE 5. OVER-CURRENT DETECTION FAULT/RT 10V 0V COUNT =1 SOFT-START 4V 2V 0V OVERLOAD APPLIED COUNT =2 COUNT =3 FAULT REPORTED The OC trip point varies with MOSFET's rDS(ON) temperature variations. To avoid over-current tripping in the normal operating load range, determine the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for IPEAK > IOUT(MAX) + (I)/2, where I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled `PWM Output Inductor Selection'. INDUCTOR CURRENT OUT1 Voltage Program 0A T0 T1 T2 TIME T3 T4 FIGURE 4. OVER-CURRENT OPERATION A resistor (ROCSET) programs the over-current trip level for the PWM converter. As shown in Figure 5, the internal 200A current sink, IOCSET develops a voltage across ROCSET (VSET) that is referenced to VIN . The DRIVE signal enables the over-current comparator (OVERCURRENT). When the voltage across the upper MOSFET (VDS) exceeds VSET , the over-current comparator trips to set the over-current latch. Both VSET and VDS are referenced to VIN and a small capacitor across ROCSET helps VOCSET track the variations of VIN due to MOSFET switching. The over-current function will trip at a peak inductor current (IPEAK) determined by: I OCSET x R OCSET I PEAK = --------------------------------------------------r DS ( ON ) The output voltage of the PWM converter is programmed to discrete levels between 1.3VDC and 3.5VDC . This output (OUT1) is designed to supply the core voltage of Intel's advanced microprocessors. The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a TTL-compatible 5-bit digital-to-analog converter. The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the different combinations of connections on the VID pins. The VID pins can be left open for a logic 1 input, because they are internally pulled up to an internal voltage of about 5V by a 10A current source. Changing the VID inputs during operation is not recommended, as it could toggle the PGOOD signal and exercise the over-voltage protection. 9 HIP6021A TABLE 1. OUT1 VOLTAGE PROGRAM PIN NAME VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 NOMINAL DACOUT VOLTAGE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.00 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 R S V OUT = V BG x 1 + ------- R P COUT4 VOUT4 RS4 RP4 FIX Q5 DRIVE4 VSEN4 Q4 VOUT3 RS3 COUT3 RP3 DRIVE3 VSEN3 +3.3VIN VAUX circuitry. Left open, the SELECT pin is internally pulled `high' and the AGP voltage is regulated to 3.3V during the softstart sequence. Once complete, the gate drive is increased and the regulator becomes a simple pass circuit for the 3.3V input voltage. OUT3 and OUT4 Voltage Adjustability The GTL bus voltage (1.5V, OUT3) and the chip set and/or cache memory voltage (1.8V, OUT4) are internally set for simple, low-cost implementation in typical Intel motherboard architectures. However, if different voltage settings are desired for these two outputs, the FIX pin provides the necessary adaptability. Left open (NC), this pin sets the fixed output voltages described above. Grounding this pin allows both output voltages to be set by means of external resistor dividers as shown in Figure 6. HIP6021A FIGURE 6. ADJUSTING THE OUTPUT VOLTAGE OF OUTPUTS 3 AND 4 Application Guidelines Soft-Start Interval Initially, the soft-start function clamps the error amplifier's output of the PWM converter. This generates PHASE pulses of increasing width that charge the output capacitor(s). After the output voltage increases to approximately 70% of the set value, the reference input of the error amplifier is clamped to a voltage proportional to the SS pin voltage. The resulting output voltages start-up as shown in Figure 2. The soft-start function controls the output voltage rate of rise to limit the current surge at start-up. The soft-start interval and the surge current are programmed by the soft-start capacitor, CSS. Programming a faster soft-start interval increases the peak surge current. The peak surge current occurs during the initial output voltage rise to 70% of the set value. NOTE: 0 = connected to GND, 1 = open or connected to 5V through pull-up resistors. OUT2 Voltage Selection The AGP output voltage is internally set to one of two levels, based on the status of the SELECT pin. Grounding the SELECT pin enables the internal 1.5V regulator control 10 HIP6021A Shutdown The HIP6021A features a dedicated shutdown pin (SD). A TTL-compatible, logic high signal applied to this pin shuts down (disables) all four outputs and discharges the soft-start capacitor. Following a shutdown, a logic low signal re-enables the outputs through initiation of a new soft-start cycle. Left open this pin will asses a logic low state, due to its internal pull-down resistor, thus enabling normal operation of all outputs. The PWM output does not switch until the soft-start voltage (VSS) exceeds the oscillator's valley voltage. The references on each linear's error amplifier are clamped to the soft-start voltage. Holding the SS pin low (with an open drain or collector signal) turns off all four regulators. A multi-layer printed circuit board is recommended. Figure 7 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE nodes, but do not unnecessarily oversize these particular islands. Since the PHASE nodes are subjected to very high dV/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 2A peak currents. Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turn-off, the upper MOSFET was carrying the full load current. During the turn-off, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET or Schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. See Application Note AN9836 for evaluation board drawings of the component placement and the printed circuit board layout of a typical application. There are two sets of critical components in a DC-DC converter using a HIP6021A controller. The switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. The power components and the controller IC should be placed first. Locate the input capacitors, especially the highfrequency ceramic decoupling capacitors, close to the power switches. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM controller close to the MOSFETs. The critical small signal components include the bypass capacitor for VCC and the soft-start capacitor, CSS . Locate these components close to their connecting pins on the control IC. Minimize any leakage current paths from SS node, since the internal current source is only 28A. 11 PWM Controller Feedback Compensation The PWM controller uses voltage-mode control for output regulation. This section highlights the design consideration for a PWM voltage-mode controller. Apply the methods and considerations only to the PWM controller. Figure 8 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The reference voltage level is the DAC output voltage (DACOUT). The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain, given by VIN/VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FESR . Modulator Break Frequency Equations 1 F LC = --------------------------------------2 x L O x C O 1 F ESR = ---------------------------------------2 x ESR x C O The compensation network consists of the error amplifier (internal to the HIP6021A) and the impedance networks ZIN and ZFB . The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 7. Use these guidelines for locating the poles and zeros of the compensation network: HIP6021A 1. Pick Gain (R2/R1) for desired converter bandwidth 3. Place 2ND Zero at Filter's Double Pole 2. Place 1ST Zero Below Filter's Double Pole (~75% FLC) OSC PWM COMP DRIVER LO DRIVER PHASE CO VOUT VIN 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier's Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary +5VIN LIN CIN VOSC - + ZFB VE/A + ESR (PARASITIC) - ZIN REFERENCE +12V CVCC VCC GND OCSET1 Q3 DRIVE2 UGATE1 PHASE1 COCSET1 ROCSET1 Q1 LOUT1 ERROR AMP +3.3VIN DETAILED COMPENSATION COMPONENTS C2 VOUT1 LOAD C1 R2 ZFB ZIN C3 R1 R3 VOUT VOUT2 LOAD COUT2 SS CSS LGATE1 HIP6021A Q2 COUT1 CR1 COMP + FB VOUT3 COUT3 VOUT4 DRIVE3 DRIVE4 Q4 PGND Q5 COUT4 HIP6021A DACOUT LOAD LOAD FIGURE 8. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN +3.3VIN KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE Compensation Break Frequency Equations 1 F Z1 = ----------------------------------2 x R 2 x C1 1 F Z2 = -----------------------------------------------------2 x ( R1 + R3 ) x C3 1 F P1 = -----------------------------------------------------C1 x C2 2 x R 2 x --------------------- C1 + C2 1 F P2 = ----------------------------------2 x R 3 x C3 FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS Figure 9 shows an asymptotic plot of the DC-DC converter's gain vs frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 8. Using the above guidelines should yield a Compensation Gain similar to the curve plotted. The gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 9 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. FZ1 100 80 60 GAIN (dB) 40 20 0 -20 -40 -60 R2 20 log ------- R1 MODULATOR GAIN 10 100 FZ2 FP1 FP2 OPEN LOOP ERROR AMP GAIN V IN 20 log ----------- V PP COMPENSATION GAIN FLC 1K FESR 10K 100K 1M CLOSED LOOP GAIN 10M FREQUENCY (Hz) FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN 12 HIP6021A Component Selection Guidelines Output Capacitors The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements. Additionally, the PWM converters require an output capacitor to filter the current ripple. The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demands. V IN - V OUT V OUT I = ------------------------------- x --------------FS x L V IN V OUT = I x ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values increase the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6021A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the post-transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O x I TRAN t RISE = ------------------------------V IN - V OUT L O x I TRAN t FALL = -----------------------------V OUT PWM Output Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR determines the output ripple voltage and the initial voltage drop following a high slew-rate transient's edge. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitors The important parameters for the bulk input capacitors are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 of the summation of the DC load current. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For a through-hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. Linear Output Capacitors The output capacitors for the linear regulators provide dynamic load current. The linear controllers use dominant pole compensation integrated into the error amplifier and are insensitive to output capacitor selection. Output capacitors should be selected for transient load regulation. PWM Output Inductor The PWM converter requires an output inductor. The output inductor is selected to meet the output voltage ripple requirements and sets the converter's response time to a load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: 13 HIP6021A MOSFET Considerations The HIP6021A requires 5 external transistors. Two N-Channel MOSFETs are used in the synchronous-rectified buck topology of PWM1 converter. It is recommended that the AGP linear regulator pass element be a N-Channel MOSFET as well. The GTL and memory linear controllers can also each drive a MOSFET or a NPN bipolar as a pass transistor. All these transistors should be selected based upon rDS(ON) , current gain, saturation voltages, gate supply requirements, and thermal management considerations. +12V VCC +5V OR LESS HIP6021A UGATE PHASE Q1 NOTE: VGS VCC -5V Q2 CR1 NOTE: VGS VCC - + LGATE PGND GND PWM MOSFETs In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty factor (see the equations below). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. The equations below assume linear voltage-current transitions and do not model power loss due to the reverserecovery of the lower MOSFET's body diode. The gatecharge losses are dissipated by the HIP6021A and don't heat the MOSFETs. However, large gate-charge increases the switching time, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. I O x r DS ( ON ) x V OUT I O x V IN x t SW x F S P UPPER = ----------------------------------------------------------- + ---------------------------------------------------V IN 2 I O x r DS ( ON ) x ( V IN - V OUT ) P LOWER = -------------------------------------------------------------------------------V IN 2 2 FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION Rectifier CR1 is a clamp that catches the negative inductor swing during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency could drop one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage. Linear Controller Transistors The main criteria for selection of transistors for the linear regulators is package selection for efficient removal of heat. The power dissipated in a linear regulator is: P LINEAR = I O x ( V IN - V OUT ) Select a package and heatsink that maintains the junction temperature below the rating with a the maximum expected ambient temperature. When selecting bipolar NPN transistors for use with the linear controllers, insure the current gain at the given operating VCE is sufficiently large to provide the desired output load current when the base is fed with the minimum driver output current. The rDS(ON) is different for the two equations above even if the same device is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Figure 10 shows the gate drive where the upper MOSFET's gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. The lower gate drive voltage is +12VDC. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC. 14 HIP6021A HIP6021A DC-DC Converter Application Circuit Figure 11 shows an application circuit of a power supply for a microprocessor computer system. The power supply provides the microprocessor core voltage (VOUT1), the AGP bus voltage (VOUT2), the GTL bus voltage (VOUT3), and the memory voltage (VOUT4) from +3.3V, +5VDC, and +12VDC. For detailed information on the circuit, including a Bill-ofMaterials and circuit board description, see Application Note AN9836. Also see Intersil's web page (http://www.intersil.com). +12VIN L1 +5VIN GND 1H C1-6 + 6x1000F C7 1F VCC C8 1000pF C9 1F FAULT/RT +3.3VIN 28 13 16 R1 23 8 OCSET PGOOD 1.0K POWERGOOD VAUX DRIVE2 VOUT2 (3.3VIN OR 1.5V) VSEN2 Q3 HUF76121D3S 1 10 27 26 UGATE PHASE Q1, 2 2xHUF76143S3S L2 4.2H VOUT1 (1.3V-3.5V) + C10, 11 2x1000F 25 24 LGATE PGND VSEN1 FB C21 10pF R3 1.62K C12-19 + 8x1000F R2 10.2K TYPEDET SELECT 11 22 U1 HIP6021A Q4 HUF76107D3S VOUT3 (1.5V) + DRIVE3 VSEN3 C23, 24 2x1000F 18 19 21 C20 0.22F 20 COMP 7 Q5 HUF76107D3S VOUT4 (1.8V) + C25, 26 2x1000F DRIVE4 VSEN4 SD FIX VID0 C22 2.7nF R4 150K R5 499K 15 14 9 2 17 GND 6 VID1 VID2 5 4 VID3 3 12 VID4 SS C27 0.1F FIGURE 11. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM 15 HIP6021A Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 28 0o MAX 2.65 0.30 0.51 0.32 18.10 7.60 10.65 0.75 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 0.394 0.01 0.016 28 0o MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 0.419 0.029 0.050 8o A1 B C D E e H C e B 0.25(0.010) M C AM BS A1 0.10(0.004) 0.05 BSC 1.27 BSC h L N NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 100 Irvine, CA 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7946 EUROPE Intersil Europe Sarl Ave. William Graisse, 3 1006 Lausanne Switzerland TEL: +41 21 6140560 FAX: +41 21 6140579 ASIA Intersil Corporation Unit 1804 18/F Guangdong Water Building 83 Austin Road TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433 16 |
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